1. Field of the Invention
The present invention relates to a delay-locked loop and, more particularly, to the delay settings for a delay-locked loop implementation that has increased precision and a wide range of operation.
2. Description of the Related Art
A delay-locked loop (DLL) is a circuit that outputs a delayed clock signal that is delayed from and in phase with a reference clock signal. FIG. 1 shows a schematic diagram that illustrates a conventional DLL 100. As shown in FIG. 1, DLL 100 includes a voltage-controlled delay line (VCDL) 110 that receives a reference clock signal VCLK and a control voltage VCNTL, and outputs a delayed clock signal VDCK that is a delayed version of the reference clock signal VCLK. The amount of delay, in turn, is defined by the magnitude of the control voltage VCNTL.
As further shown in FIG. 1, DLL 100 also includes a phase detector 112 that detects the difference in phase between the reference clock signal VCLK and the delayed clock signal VDCK. When the reference clock signal VCLK leads the delayed clock signal VDCK, phase detector 112 asserts an up signal VUP.
On the other hand, when the reference clock signal VCLK lags the delayed clock signal VDCK, phase detector 112 asserts a down signal VDN. When the reference clock signal VCLK and the delayed clock signal VDCK are in phase, phase detector 112 asserts neither the up signal VUP nor the down signal VDN.
In addition, DLL 100 also includes a charge pump 114 that outputs a pump voltage VPM. Pump 114 increases the pump voltage VPM when the up signal VUP is asserted, and decreases the pump voltage VPM when the down signal VDN is asserted. The pump voltage VPM is unchanged when both the up signal VUP and the down signal VDN are de-asserted. Further, DLL 100 includes a filter 116 that filters the voltage output from pump 114 to provide the control voltage VCNTL.
In operation, phase detector 112 continues to adjust the pump voltage VPM via the up and down signals VUP and VDN, and thereby the control voltage VCNTL, until VCDL 110 adjusts the timing of the delayed clock signal VDCK to be in phase with the reference clock signal VCLK. When the delayed clock signal VDCK is in phase with the reference clock signal VCLK, DLL is locked and phase detector 112 inhibits the up and down signals VUP and VDN until the clock signals VDCK and VCLK fall out of lock.
DLLs are typically formed to accommodate a range of signal periods. One problem with DLLs, however, is that it is difficult to form a DLL that can accommodate a wide range of signal periods. For example, it is difficult to track clocks with periods varying from in 1 nS to 20 nS as the DLL should be able to delay the reference clock signal VCLK by a minimum of 1 nS and a maximum of 20 nS.
Another problem with DLLs is that it is difficult to obtain high precision (granularity) such that the delay varies evenly with the control voltage VCNTL. Ideally, the minimum delay provided by the DLL corresponds with a control voltage VCNTL equal to the lower supply voltage VSS, and the maximum delay provided by the DLL corresponds with a control voltage VCNTL equal to the upper supply voltage VCC. In addition, intermediate delays ideally vary proportionally as the control voltage VCNTL varies between the lower and upper supply voltages VSS and VCC.
In addition, DLLs are typically sensitive to temperature and process variations which, in turn, can prevent a DLL from locking on all frequencies. Thus, there is a need for a delay locked loop with increased precision and range of operation that is ideally insensitive to temperature and process variations.